In the fabrication of semiconductor wafers, sheet resistance has become a driving issue, particularly in current limit/regulation concerns. This has become of particular significance in cold-cathode tip operation in field emission technology as well as in the fabrication of row line formations associated with memory devices, such as Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM) and the like. For instance, flat panel displays require well defined resistors to control the cathode emission tip current during operation. Controlling the sheet resistance of the material used is an important aspect in defining the required resistance.
Sheet resistance is defined as the resistance measured across the conductive layer which may typically be positioned across the top of a transistor structure. For example, it is typical in DRAM fabrication to use silicides, such as tungsten silicide (WSi.sub.x) and titanium silicide (TiSi.sub.x) to form a rowline, which also serves as a gate to an active transistor structure. Standard annealing process steps in forming the conductive layer, such as tungsten silicide (WSi.sub.x), superjacent the transistor structure have yielded lowered values of sheet resistance.
Sheet resistance directly correlates with propagation delay, switching speed and device size. This is supported by the principal that the lower the sheet resistance, the greater the number of electrons that will flow. Thus, the size, capacity and speed are all dependent on the electrical characteristics of the conductive layer.
In semiconductor fabrication it is desirable to be able to control the sheet resistance of a conductive and/or insulating layer. However, producing a material that possesses a tight resistance tolerance using a process that can be tightly controlled is a major challenge to process engineers. An effective and controllable method to produce a material having a specific sheet resistance would prove to be very beneficial to many semiconductor fabrication processes.